module dataInDeMuxer16 (
    input wire clk,
    input wire rst,
    input wire write_en_in,                             //端口的写入使能
    input wire [5:0] data_priority_in,                  //端口写入数据包的写入优先级
    input wire [9:0] data_size_in,                      //端口写入数据包的长度
    input wire [15:0] data_target_port_in,              //端口写入数据包的目的端口
    output reg [15:0] write_en_out,                     //端口的写入使能
    output reg [5:0] data_priority_out [0:15],          //端口写入数据包的写入优先级
    output reg [9:0] data_size_out [0:15]               //端口写入数据包的长度
);
    
    integer i;

    //数据分发
    always @(posedge clk) begin
        if (rst) begin
            //复位信号拉高时，将所有的使能信号拉低
            write_en_out <= 16'h0000;
            for (i=0; i<16; i=i+1) begin
                data_priority_out[i] <= 0;
                data_size_out[i] <= 0;
            end
        end
        else begin
            //按照target_port将数据转发到对应端口
            if (write_en_in) begin
                write_en_out <= data_target_port_in;
                for (i=0; i<16; i=i+1) begin
                    data_priority_out[i] <= data_priority_in;
                    data_size_out[i] <= data_size_in;
                end
            end
            else begin
                write_en_out <= 16'h0000;
            end
        end
    end
endmodule